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Pin In Hole/ Surface Mount Technology Hybrid Surface Insulation Resistance Test Card

IP.com Disclosure Number: IPCOM000120134D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Best, DP: AUTHOR [+3]

Abstract

This article presents a working Pin-In-Hole (PIH)/Surface Mount Technology (SMT) hybrid card design which can be used to perform Surface Insulation Resistance (SIR) testing with minimal impact to test apparatus currently available. The card design results in minimal raw card costs, can be populated with any SMT components of generic size, regardless of internal electronic circuitry, and is wired in such a way so as to provide a maximum number of SIR risk sites for worse-case analysis.

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Pin In Hole/ Surface Mount Technology Hybrid Surface Insulation Resistance
Test Card

      This article presents a working Pin-In-Hole (PIH)/Surface
Mount Technology (SMT) hybrid card design which can be used to
perform Surface Insulation Resistance (SIR) testing with minimal
impact to test apparatus currently available.  The card design
results in minimal raw card costs, can be populated with any SMT
components of generic size, regardless of internal electronic
circuitry, and is wired in such a way so as to provide a maximum
number of SIR risk sites for worse-case analysis.

      The hybrid SIR card is shown in the figure.  It is composed of
standard, two-sided FR-4 material of dimensions 3.8" X 4.1".  The
card contains sites for the population of the following SMT
components:  2 - 160 pin SMT Quad Flat Pack (QFP) modules, 1 - 144
pin SMT QFP module, 3 - 2220 SMT chip capacitors.  All QFP modules
contain pads on .025" pitch.  Additionally, the card has a 5 X 10
array of .040" holes to be used for PIH component population.  This
menu of components provides a worse-case set of conditions for
cleaning typically seen on hybrid card assemblies.

      Along with the component sites, IR circuitry is etched into the
card to assess card cleanliness in various areas under the
components.  Through-hole vias are located under the QFPs on .050
spacings.  These vias provide 92 total SIR risk sites underneath the
QFPs on the card.  Additionally, located under each...