Browse Prior Art Database

Delay Logic

IP.com Disclosure Number: IPCOM000120196D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 33K

Publishing Venue

IBM

Related People

Kugel, L: AUTHOR [+2]

Abstract

Disclosed is a form of logic in which 0 and 1 are distinguished by the delay of a signal with respect to a reference signal. The novel aspect is that, instead of using magnitude to denote 0 or 1, a 0 or 1 in delay logic is determined by whether a signal occurs before or after a reference signal.

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Delay Logic

      Disclosed is a form of logic in which 0 and 1 are distinguished
by the delay of a signal with respect to a reference signal.  The
novel aspect is that, instead of using magnitude to denote 0 or 1, a
0 or 1 in delay logic is determined by whether a signal occurs before
or after a reference signal.

      Single rail delay logic works as follows:

      A reference signal is sent down one signal line.  Data signals
are sent down other signal lines, one data bit per line.  If a data
signal for a bit arrives before the reference signal, that data bit
is a 1.  If a data signal arrives after the reference signal, that
data bit is a 0.

      Dual rail delay works as follows:

      Two signal lines are required to each bit.  If the signal from
line 1 arrives before the signal from line 2, then the bit is a 1.
If the signal from line 2 arrives before line 1, then the bit is a
0.

      Delay logic has an advantage for long distance communication
with weak signals.  Delay between a signal and reference signal
propagating through air, a vacuum, copper wire, optical cables, or
any other passive medium can be set at the sending end and is not
affected by noise.  The signal magnitude is unimportant, the signal
must only be detected. Thus delay logic is highly immune to changes
in the signal level.

      Disclosed anonymously.