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Method of Fabricating a Schottky Collector Bipolar Transistor

IP.com Disclosure Number: IPCOM000120218D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Akbar, S: AUTHOR [+4]

Abstract

This article describes a method of fabricating a Schottky Collector Transistor with a normal emitter-up structure. An epitaxial silicide collector is used upon which a low-temperature epitaxial base can be grown. The process steps are described as follows for the case of a PNM transistor: (1) About 80 nm of epitaxial cobalt disilicide are grown on a p-Si (100) substrate using Molecular Beam Epitaxy or cobalt ion implantation followed by annealing. A 50 nm intrinsic Si buffer layer is grown on top of the CoSi2 . 100 nm CVD Si02 is then deposited on the buffer i-Si layer, and the oxide window is opened lithographically. The wafer is then transferred to a Low Temperature Epitaxial reactor where 80 nm of 1E17 n-Si linker layer and 100 nm Si02 and 100 nm Si3N4 dielectric stack is deposited by PECVD. (2) Fig.

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Method of Fabricating a Schottky Collector Bipolar Transistor

      This article describes a method of fabricating a Schottky
Collector Transistor with a normal emitter-up structure.  An
epitaxial silicide collector is used upon which a low-temperature
epitaxial base can be grown.  The process steps are described as
follows for the case of a PNM transistor:
   (1)  About 80 nm of epitaxial cobalt disilicide are grown on a
p-Si (100) substrate using Molecular Beam Epitaxy or cobalt ion
implantation followed by annealing.  A 50 nm intrinsic Si buffer
layer is grown on top of the CoSi2 . 100 nm CVD Si02 is then
deposited on the buffer i-Si layer, and the oxide window is opened
lithographically.  The wafer is then transferred to a Low Temperature
Epitaxial reactor where 80 nm of 1E17 n-Si linker layer and 100 nm
Si02 and 100 nm Si3N4 dielectric stack is deposited by PECVD.
   (2)  Fig. 1 shows the opened base window by RIE through the Si3N4,
Si02 and poly into the linker n-Si layer.  Some overetch is allowed,
thereby eliminating the need for an RIE barrier.
   (3)  To fabricate the extrinsic base sidewall, a thin thermal
oxide is grown, followed by a stack of 100 nm nitride and 100 nm TEOS
oxide.  This insulator stack is plasma etched to yield a 150-nm-wide
sidewall at the extrinsic base edge.  This sidewall is then used to
define the intrinsic base window by RIE through the n-linker and the
50 nm i-Si buffer layers.  The CF4 etch is stopped selectively (10...