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High Performance FET Structure Made Using Medium to Low Temperature Epitaxy

IP.com Disclosure Number: IPCOM000120219D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 79K

Publishing Venue

IBM

Related People

Chu, JO: AUTHOR [+5]

Abstract

Using epitaxial growth reactors, it is possible under certain conditions to grow monocrystalline silicon 4 on areas of single crystal substrate 3 and poly Si 5 on areas of oxide 1 located on the same substrate 2 (Fig. 1).

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High Performance FET Structure Made Using Medium to Low Temperature
Epitaxy

      Using epitaxial growth reactors, it is possible under
certain conditions to grow monocrystalline silicon 4 on areas of
single crystal substrate 3 and poly Si 5 on areas of oxide 1 located
on the same substrate 2 (Fig. 1).

      If such a layer is treated appropriately, it can be used to
form an FET with greatly reduced perimeter and area components of
junction capacitance (Fig. 2A).

      This results from forming a large portion of the source/drain
diffusion regions 6 (which are normally made in single crystal
silicon 2, as in Fig. 2B, for the conventional device) in the poly Si
5 grown on oxide 1. Because the contact holes 8 no longer need to
resist fully on the monocrystalline diffusion region 7 to make
contact to it, the region 9 of the diffusion mode in single crystal
Si (where the capacitance exists) can be much smaller.  This will
contribute to an improved performance.

      Further enhancements to performance may come about with the use
of reduced temperature growth for the process of growing the
poly/single crystal Si layer 5/4.  The use of lower temperature
growth means that dopant redistribution from the original substrate 2
upward into the newly grown Si 4 would be minimal.  If the growth
results in a thin intrinsic or near intrinsic layer of single crystal
Si for the channel region, the mobility through the channel would
improve.  The reduced doping also dec...