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Means for Implementing Optical Interconnections for Parallel Processors

IP.com Disclosure Number: IPCOM000120220D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 129K

Publishing Venue

IBM

Related People

Green, PE: AUTHOR [+2]

Abstract

This description shows a how a broadband optical communication network can be used to interconnect parallel processors and memories. A major constraint for interconnections made from electrical conductors is that one conductor cannot carry independent transmissions concurrently at the same instant of time, although this is done in some low-speed local-area networks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Means for Implementing Optical Interconnections for Parallel Processors

      This description shows a how a broadband optical
communication network can be used to interconnect parallel processors
and memories.  A major constraint for interconnections made from
electrical conductors is that one conductor cannot carry independent
transmissions concurrently at the same instant of time, although this
is done in some low-speed local-area networks.

      We describe a system in which multiple independent
transmissions are concurrently within one optical fiber. We show how
to do this by exploiting the high bandwidth of fibers by using
transmitters of different frequencies, and by tuning receivers to
specific frequencies.  The system is based on a bus architecture that
is implemented optically by means of a star coupler.  The system not
only operates as broadcast bus, but has the additional property of
being able to broadcast all signals from all inputs to all outputs in
the same instant of time.  The connections may be made dynamically
switchable by providing frequency tunability in transmitters,
receivers or both.

      In the system described here, because all connections can be
made concurrently without conflict, the interconnection system is
high-speed and contention-free. Contention occurs only at the
receivers, rather than within the interconnection network.

      The system consists of a collection of hardware plus the
protocol required for the hardware to operate satisfactorily within a
parallel computer system.
HARDWARE DESCRIPTION

      The hardware consists of at least the following components:
1.  A star-coupler optical link that connects N inputs to N outputs,
2.  Tunable laser transmitters, at least one and possibly several per
coupler input,
3.  Tunable receivers, at least one and possibly several per coupler
output,
4.  N independent processors, and
5.  N memory modules.

      The system is configured into N nodes, such that each node
contains one processor, one memory, one set of transmitters, and one
set of receivers. Each set of transmitters at a node is connected to
one input of the star coupler, and each set of receivers at a node is
connected to one output of the star coupler.
TWO PROTOCOLS FOR SIGNALING

      The basic purpose of the interconnection network is to support
point-to-point access from any computer to any memory.  Since a
memory can service only one computer at a time, a protocol must
provide a means for a multiplicity of computers to post a request at
a single memory, for the memory to select one such request, for the
memory to signal the corresponding requester that the request has
been granted, and for the requester to then execute the request which
could either be a READ or a WRITE of data.

      There are two protocols described here:
1.  Time-frequency selection, and
2.  Frequency-frequency selection.

      Time-frequency selection - For time-frequency...