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Analog Electrical Alignment Structure for Emitter-to-Extrinsic Base Overlay

IP.com Disclosure Number: IPCOM000120222D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 132K

Publishing Venue

IBM

Related People

Martin Jr, B: AUTHOR [+2]

Abstract

This invention allows overlay alignment between two critical levels needed to form npn transistors to be determined using electrical measurements. The two critical levels are those used to form (1) the extrinsic base and (2) emitter of npn transistors in a double poly base bipolar technology. The preferred mode of operation for determining alignment is inverse, although normal operation should work just as well.

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Analog Electrical Alignment Structure for Emitter-to-Extrinsic Base
Overlay

      This invention allows overlay alignment between two
critical levels needed to form npn transistors to be determined using
electrical measurements.  The two critical levels are those used to
form (1) the extrinsic base and (2) emitter of npn transistors in a
double poly base bipolar technology.  The preferred mode of operation
for determining alignment is inverse, although normal operation
should work just as well.

      Refer to Fig. 1 for layout and cross-sectional views of the
structure.

      The structure consists of two side-by-side npn transistors,
which are preferably operated in inverse mode. With perfect alignment
the transistors are mirror images of each other (when reflection
takes place through a line midway between the two).  The critical
dimension of the structure is the width of the extrinsic base.  One
side of the width of the extrinsic base is defined by the emitter
level, the other sides are defined by the extrinsic base mask level.
Overall, three sides of the extrinsic base are defined by the
extrinsic base level, and one side is defined by the emitter mask
level.

      In a similar manner, one side of the width of the emitter is
defined by the emitter level; the other sides are defined by the
extrinsic base level.  Overall, in this case, three sides of the
emitter are defined by the extrinsic base level, and one side is
defined by the emitter mask level.

      The structure is designed so that with perfect alignment the
width of extrinsic base exactly equals the width of the emitter.
When misalignment occurs, the width of the extrinsic base gets
larger, and the width of the emitter gets smaller, on one of the
transistor pair, while just the opposite happens on the other of the
pair.

      These usual transistors are designed so that extrinsic base
current dominates the total base current when the devices are
operated in inverse mode.  This is done by choosing an aspect ratio,
for the extrinsic base, which optimizes sensitivity to misalignment.

      In actual practice, two sets of transistor pairs would be used;
one, normally having both transistors perfectly aligned, the other
with intentional misalignment (say, 0.5 micrometers).

      Inverse DC characteristic measurements (Gummel plot) are made
on each of the four transistors.  From the inverse base current
characteristic, ideal base current saturation currents are
calculated.  The ideal saturation currents can be written in terms of
injection current components as follo...