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Deterministic Test Generation for Transition Faults

IP.com Disclosure Number: IPCOM000120224D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 100K

Publishing Venue

IBM

Related People

Forlenza, DO: AUTHOR [+4]

Abstract

This article proposes a way to generate a two-pattern transition fault test in a single pass. This method is more efficient than the existing two-pass approach, can identify and avoid adjacent latch dependency, and can be controlled to minimize conflicting states between the two patterns.

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This is the abbreviated version, containing approximately 52% of the total text.

Deterministic Test Generation for Transition Faults

      This article proposes a way to generate a two-pattern
transition fault test in a single pass.  This method is more
efficient than the existing two-pass approach, can identify and avoid
adjacent latch dependency, and can be controlled to minimize
conflicting states between the two patterns.

      The transition fault is an efficient way to model delay or AC
defects.  It is defined as a defect that delays either a rising
(slow- to-rise) or falling (slow-to-fall) transition on any input or
output of a logic gate.  In general, two distinct consecutive
patterns are required to detect a transition fault.  The first
pattern places the initial transition value at the point of the fault
and is called the initialization pattern.  The second pattern places
the final transition value at the point of the fault and propagates
the effect to a timed measurable point.  This pattern is called the
transition propagation pattern and is identical to the pattern that
detects the corresponding stuck fault.

      Normally, test generation for transition faults creates these
two patterns independently.  There are two serious problems that
result from independent test generation.  The first problem is the
adjacent latch dependency.  Generally, transitions are launched on
LSSD latches by pulsing the last scan clock (B-clock) of the shift
register load.  This results in a dependency between the values that
can be allowed on adjacent latches for the two patterns.  To
illustrate this problem, consider the slow-to-fall fault on the
second input of the OR gate in the figure.  The first pattern
requires a '1' placed on the L2 of SRL1.  The second pattern requires
a '0' on L2 of SRL2 to propagate it to an observable point.  It would
appear that this is a successful test.  However, if the scan-in is
used to place the initial value of '1' on the L2 of SRL1, it will
also place a '1' on the L1 of SRL2.  This prevents the '0' value on
the L2 of SRL2 that is required for the second pattern when the
succeeding B scan clock is pulsed.  To guarantee a successful test of
a transition fault, this condition must be identified during test
generation and avoided whenever possible.

      The second problem occurs when the test is being used as the
source of a set of weights in weighted random pattern (WRP) test
generation.  Opposing values...