Browse Prior Art Database

Tight Tolerance Boron-Implanted Polysilicon Resistor Process

IP.com Disclosure Number: IPCOM000120226D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 104K

Publishing Venue

IBM

Related People

Acocella, JE: AUTHOR [+2]

Abstract

This article describes a process for obtaining tight tolerance, sidewall resistors (providing increased VLSI chip circuit density) through the use of boron-doped base polysilicon. Formed by sidewall image transfer (SIT) techniques that can produce smaller linewidths with tighter control than obtainable from conventional photolithography, the disclosed process yields resistors that occupy less space than those formed from single crystal silicon. The disclosed process can be integrated into existing advanced transistor fabrication processes without need for additional process steps provided a suitable reactive ion etching (RIE) process is used during the oxide etch before base polysilicon deposition.

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This is the abbreviated version, containing approximately 52% of the total text.

Tight Tolerance Boron-Implanted Polysilicon Resistor Process

      This article describes a process for obtaining tight
tolerance, sidewall resistors (providing increased VLSI chip circuit
density) through the use of boron-doped base polysilicon.  Formed by
sidewall image transfer (SIT) techniques that can produce smaller
linewidths with tighter control than obtainable from conventional
photolithography, the disclosed process yields resistors that occupy
less space than those formed from single crystal silicon.  The
disclosed process can be integrated into existing advanced transistor
fabrication processes without need for additional process steps
provided a suitable reactive ion etching (RIE) process is used during
the oxide etch before base polysilicon deposition.

      The boron implanted polysilicon process for forming tight
tolerance sidewall resistors is similar in some respects to that
outlined in (*), which employed arsenic-doped emitter polysilicon to
the same end, and is compatible with existing advanced transistor
fabrication practice.  Existing single crystal silicon resistor
formation steps are omitted from the fabrication process following
completion of collector-reach-through formation, and the following
steps undertaken beginning with polysilicon base formation:

      Fig. 1 shows the resistor 1 and transistor 2 regions of the
substrate after coating by multilayer resist (MLR), masking, exposure
and development.  Mask provisions should include the resistor mandrel
3 shown over the isolation oxide (ROI) 4.

      Following resist development, the oxide is reactive ion etched
(RIE) all the way through to transistor region silicon 2, using an
RIE gas, such as CHF3/Ar and omitting any oxide wet etch.  After
resist strip, the polysilicon deposition 5, extrinsic base implant,
CVD oxide 6 and resist coating steps proceed, followed...