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Improved Bit Sparing Technique Yields Faster Memory Array Access

IP.com Disclosure Number: IPCOM000120233D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 132K

Publishing Venue

IBM

Related People

Norgaard, SP: AUTHOR

Abstract

When a large memory array is used in a computing system, some form of redundancy is needed to detect and fix errors in the array (data integrity and fewer Repair Actions). Parity is the most common form of error detection but it has no correcting ability. Error Correction Codes (ECCs) are popular in certain applications because they can be made very powerful (detect and correct several bits in error). The implementation of these powerful ECC algorithms requires a lot of logic and extra memory. It also puts constraints on usability. For example, they do not allow partial word writes (writing to just a portion of the ECC word). This has to be done with a time-consuming "read-modify- write" cycle.

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Improved Bit Sparing Technique Yields Faster Memory Array Access

      When a large memory array is used in a computing system,
some form of redundancy is needed to detect and fix errors in the
array (data integrity and fewer Repair Actions). Parity is the most
common form of error detection but it has no correcting ability.
Error Correction Codes (ECCs) are popular in certain applications
because they can be made very powerful (detect and correct several
bits in error). The implementation of these powerful ECC algorithms
requires a lot of logic and extra memory.  It also puts constraints
on usability.  For example, they do not allow partial word writes
(writing to just a portion of the ECC word).  This has to be done
with a time-consuming "read-modify- write" cycle.

      Another method called "bit sparing" or "reconfigure" is a
compromise between the two methods above.  It uses parity for error
detection and spare memory for error correction. Since the most
common failure mode for a memory is module kill (the whole module
goes bad), this method removes a failing memory module by
reconfiguring a spare in its place.

      Bit sparing technique is shown in Fig. 1.  In Fig. 1, it can be
seen that the data to be stored (bits 0 to 7 and Parity) comes in
on the left and the data retrieved goes out on the right.  The memory
array (M0 to M9) is in the middle. The group of A*OR logic gates and
the control register (CNTL REG) with decodes represents the
reconfigure logic.  The decodes that come out of the control register
select which data bit will be gated into the spare module (M9) and
they select which output data bit (if any) gets substituted with the
spare.

      In normal operation, all of the memory modules are good and the
spare is not used.  If one of the modules fails, the control register
is loaded with a value that generates a decode corresponding to that
bit.  The decodes are used to route the data bits through the correct
A*OR gates.  Then, for write operations, the data bit for the failing
module will be routed into the spare module instead, and, for read
operations, the data from the spare will be routed to that bit's
output.

      The problem with this implementation is the timing difference
between normal operation and reconfigured operation.  In normal
operation, the data flows through the circuit without much delay from
the reconfigure logic. However, in reconfigured operation, there are
two areas where the signal timings are delayed.  First, for writes,
the data has to be funneled through a large A*OR gate before it gets
into the spare.  A large A*OR, l...