Browse Prior Art Database

Hardware Reset With Microcode Warning Period

IP.com Disclosure Number: IPCOM000120237D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Fawcett, BW: AUTHOR [+3]

Abstract

Described is a hardware reset design. When the reset mechanism is invoked, a hardware reset is guaranteed to take place regardless of the state the controlling software is in. However, it gives the software a pre-warning of the reset that will take place shortly. This allows the software to perform some clean-up operations, if desired, before the hardware is reset.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

Hardware Reset With Microcode Warning Period

      Described is a hardware reset design.  When the reset
mechanism is invoked, a hardware reset is guaranteed to take place
regardless of the state the controlling software is in.  However, it
gives the software a pre-warning of the reset that will take place
shortly.  This allows the software to perform some clean-up
operations, if desired, before the hardware is reset.

      The figure shows the hardware configuration needed to implement
this reset mechanism.  When a reset request 1 is detected by the
card's hardware, it is posted to the processor at the highest
priority level interrupt 4.  The reset request 1 also activates a
hardware time delay element 5.  This element, once activated, will
wait the set time delay, and then activate the real hardware reset
mechanism 6,7.  This mechanism 6,7 then performs the normal hardware
resets and flushes.  This delay element 5 also has a capability of
being reloaded to the initial time setting via a Timer Reload signal
8.  The delay element 5 cannot be disabled, but this reload
capability allows for multiple time delay intervals to be requested
if needed.

      The software necessary to implement this invention is in the
interrupt handler for the highest level interrupt 4. Typically, the
first operation the handler performs is to save away all important
information into a predetermined location in memory, assuming memory
is not affected by the hardware reset.

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