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Browse Prior Art Database

Single-Event Upset-Hardened SRAM Cells

IP.com Disclosure Number: IPCOM000120248D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Haddad, NF: AUTHOR [+2]

Abstract

This article describes integrated electronic circuits, e.g., SRAMS, which are subject to hits by heavy ions, i.e., ions heavier than atomic number 2, such as oxygen, argon, iron, etc., that can disrupt normal circuit performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Single-Event Upset-Hardened SRAM Cells

      This article describes integrated electronic circuits,
e.g., SRAMS, which are subject to hits by heavy ions, i.e., ions
heavier than atomic number 2, such as oxygen, argon, iron, etc., that
can disrupt normal circuit performance.

      These hits, called single events, hit on or near a
reverse-biased circuit node, causing a voltage transient situation
with resultant information loss.

      The figures show high density, single-event hardened CMOS SRAM
memory cells.  These hardened cells are provided with the addition of
four transistors to the basic cell: TA, TB, TC, and TD.  TC and TD
are PFETs which function as MOS switching capacitors to create a
capacitance imbalance in the cell, hardening it against single-event
hits.