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High Speed Increment Function or Decrement Function with Load/Hold Function in Altera Field Programmable Gate Array

IP.com Disclosure Number: IPCOM000120264D
Original Publication Date: 1997-Jan-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 8 page(s) / 181K

Publishing Venue

IBM

Related People

Benayoun, A: AUTHOR [+2]

Abstract

Incrementer: -- VHDL DESIGN FOR 8 Bits INCREMENTER WITH LOAD AND HOLD -- Library IEEE; Use IEEE.std_logic_1164.all; Use IEEE.std_logic_unsigned.

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High Speed Increment Function or Decrement Function with Load/Hold
Function in Altera Field Programmable Gate Array

      Incrementer:
  --      VHDL DESIGN FOR 8 Bits INCREMENTER WITH LOAD AND HOLD  --
  Library IEEE;
  Use IEEE.std_logic_1164.all;
  Use IEEE.std_logic_unsigned.all;
  Entity INCREMENTER_8 is
  Port (
     RESET       : in  std_logic                 := '0'       ;
     CLOCK       : in  std_logic                 := '0'       ;
     LOAD        : in  std_logic                 := '0'       ;
     HOLD        : in  std_logic                 := '0'       ;
     LOAD_VALUE  : in  std_logic_vector(0 to 7)  := "00000000";
     INC_8_OUT   : out std_logic_vector(0 to 7)
    );
  End    INCREMENTER_8;
  Architecture INCREMENTER_8_A of INCREMENTER_8 is
    Signal INC_8       : std_logic_vector(0 to 7) := "00000000";
  Begin
  Process(CLOCK,RESET)
  Begin
  If (RESET = '1')
  Then         INC_8 <= "00000000";
  Else
     If (CLOCK'event and CLOCK='1')
     Then  If    (LOAD = '1')   Then INC_8 <= LOAD_VALUE;
           Elsif (HOLD = '1')   Then INC_8 <= INC_8;
                                Else INC_8 <= INC_8 + 1;
           End If;
     End If;
  End If;
  End Process;
  INC_8_OUT <= INC_8;
  End INCREMENTER_8_A;
             Fig. 1  Incrementer with Hold/Load in VHDL

      If SYNOPSYS "X = X + 1" or "X = X - 1" is synthesized, using
the Flex 10K library, the FLEX_INC (Increment Function) or the
FLEX_DEC (Decrement Function) macro functions will be invoked
respectively.

      MAX+PLUS II will then map these macro functions into Altera
Logic Elements (LE) using the  Arithmetic Mode.   The Load/Hold
function is then realized using extra LE resources.

      22 cells are necessary to map the Incrementer or Decrementer
with a Load/Hold function and the estimated speed given by a MAX+PLUS
II Timing Analyzer tool is 45 MHz.

      Figs. 1 and 3 show the most useful VHDL description of an
Incrementer and Decrementer, respectively.

      Figs. 2 and 4 present the SYNOPSYS synthesis of these VHDL
descriptions.  One can see the "INCREMENTER_8_FLEX_INC_MOD_8_0" and
the "DECREMENTER_8_FLEX_DEC_MOD_8_0" macrofunctions.  The Load/Hold
function is realized in parallel to the Incrementer or Decrementer
function.

      Decrementer:
  --  VHDL DESIGN FOR 8 Bits DECREMENTER WITH LOAD AND HOLD  --
  Library IEEE;
  Use IEEE.std_logic_1164.all;
  Use IEEE.std_logic_unsigned.all;
  Entity DECREMENTER_8 is
  Port (
     RESET       : in  std_logic                 := '0'       ;
     CLOCK       : in  std_logic                 := '0'       ;
     LOAD        : in ...