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High Speed Programmable Shift Register in Altera Field Programmable Gate Arrays

IP.com Disclosure Number: IPCOM000120266D
Original Publication Date: 1997-Jan-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 8 page(s) / 139K

Publishing Venue

IBM

Related People

Loison, JP: AUTHOR

Abstract

Disclosed is a method of using the MAX+PLUS II Cell mapping Up/Down Counter Mode and change the equations inside the dedicated LUTs.

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High Speed Programmable Shift Register in Altera Field Programmable
Gate Arrays

      Disclosed is a method of using the MAX+PLUS II Cell mapping
Up/Down Counter Mode and change the equations inside the dedicated
LUTs.

The two primitives used in this mode are:
  o  The FLEX_COUNT primitive, for Increment or Decrement
      generation.
  o  The FLEX_CARRY_COUNT primitive, for Carry generation.
  Equations are respectively:
    (((Carry_In xor Q) and ENA) or (Q and not ENA)) and LOAD)
    or (DATA and not LOAD)
        Carry_In and (UP/D notxor COUNT)

In the proposed implementation:
  o  The first primitive (FLEX_COUNT) is used to perform the
      Hold/Load functions with the ENA, LOAD, and DATA Inputs.
  o  The second primitive (FLEX_CARRY_COUNT) is used to route
      the Q signal to the next Cell.
       The UP/D input can be used to select either the Q signal
      from the current Cell or the Q signal from one of the
      previous Cells carried by Carry_In Input.
       In each of the two primitives, a MUX function is
      implemented with the following equations:
  New equations:
    (((Q and ENA) or (Carry_In and not ENA)) and LOAD)
     or (DATA and not LOAD)
       (Q and UP/D) or (Carry_In and not UP/D)

Cascading these new Cells allows you to have the following functions
for a wide register:
  o  Multiple or Single bit Load
  o  Multiple or Single bit Hold
  o  Shift by 1, 2, .., n.

Each of these functions is selected for each Cell by the LOAD, ENA,
UP/D Inputs.

Example of register configuration - From Fig. 2:

Applying the following patterns to the Inputs:
       LOAD(n,n+1,n+2)   HOLD(n,n+1,n+2)   SEL(n,n+1,n+2)
       011               010               010
       Will:
  1.  Load the DATA(n) into the register Q(n)
       Route the previous Q(n) value to SHIFT(n)
  2.  Hold the Q(n+1) register value
       Route the SHIFT(n) value to SHIFT(n+1)
  3.  Shift the SHIFT(n+1) value (corresponding to the previous
       Q(n) value) to Q(n+2) register Route the previous Q(n+2)
       value to SHIFT(n+2)

Thus being able to perform a shift function while loading or holding
data, consuming a single Cell per bit.

      Realization - The primitives FLEX_COUNT and FLEX_CARRY_COUNT
are ins...