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A 9-Way XOR Gate for Error Detection with 100% Test Coverage

IP.com Disclosure Number: IPCOM000120276D
Original Publication Date: 1991-Feb-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 44K

Publishing Venue

IBM

Related People

Milano, LC: AUTHOR

Abstract

Disclosed is a circuit for error detection which can be 100% tested, even if multiple input states cannot achieve a logical one state. (Image Omitted)

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 90% of the total text.

A 9-Way XOR Gate for Error Detection with 100% Test Coverage

      Disclosed is a circuit for error detection which can be 100%
tested, even if multiple input states cannot achieve a logical one
state.

                            (Image Omitted)

      The concept is to build a nine-way exclusive-Or circuit which
contains three additional logic Or gates and an extra input to be
used for test.  Of the several ways to build an exclusive- Or
circuit, the use of logical Or-invert and logical And gates yields
the best test coverage results. Only three logic Or gates are needed
because the circuit will be split into three-way exclusive Or's.  If
we take one input of each three-way exclusive-Or and logical Or it
with test input, then full test coverage can be achieved regardless
of limitations of input states.  This circuit is useful in
applications that have any type of exclusive-Or network where all
inputs cannot achieve a logical one state.

      If this circuit is built as a logic gate, several cells and
wires can be saved.  Today, as chips become more dense, the amount of
error detection logic will increase.  The savings of those cell and
wires will become very significant.  Also the impact of a large
amount of error detecting circuits with low test coverage can be
detrimental.  A single input Or latch can be added to the chip to
feed the test input of the above circuit and all test coverage
problems will be solved.  This will a...