Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Memory On-Chip Complement/Recomplement

IP.com Disclosure Number: IPCOM000120291D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 56K

Publishing Venue

IBM

Related People

Brearley, AW: AUTHOR [+3]

Abstract

Double bit errors in an error correction code (ECC) word are corrected by use of circuitry and a new chip initial program load (IPL) code permitting operation of complement/recomplement (C/R) for all card and other systems applications without turning the chip ECC off. While conventional large system C/R requires six system cycles, this on-chip technique requires only four cycles.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 62% of the total text.

Memory On-Chip Complement/Recomplement

      Double bit errors in an error correction code (ECC) word are
corrected by use of circuitry and a new chip initial program load
(IPL) code permitting operation of complement/recomplement (C/R) for
all card and other systems applications without turning the chip ECC
off.  While conventional large system C/R requires six system cycles,
this on-chip technique requires only four cycles.

      The new IPL code, when enabled, provides that all static random
access memory (SRAM) data bits are inverted during a fetch cycle from
the dynamic RAM (DRAM).  ECC check bits are included in the
inversion.  This allows the on-chip ECC to be left on while providing
successful C/R to the card/system.

      This operation is triggered by card logic once it has sensed
that a double error has occurred at the card/system ECC.  A chip
complement mode is turned on by an IPL command with the proper code.
A store cycle then sends complement SRAM data to the array.  A normal
store command is issued but the data in is "Don't Care".  Page mode
is not used.  A row address select (RAS) precharge is required before
the store cycle.  The chip store cycle is performed by first
disabling ECC on all quadrants.  Then, data is fetched from DRAM,
including ECC checkbits, from a specified address. Data is then
inverted and stored in an on-chip SRAM.  Data from SRAM is then
stored back to DRAM, including ECC checkbits.  New checkbits are not
gener...