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Sense Amplifier for Clocked Array

IP.com Disclosure Number: IPCOM000120292D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 41K

Publishing Venue

IBM

Related People

Wissel, L: AUTHOR

Abstract

A field-effect transistor (FET) is used in this BiCMOS sense amplifier to rapidly restore a bit line. The circuit achieves high performance and low power dissipation on clocked arrays while also providing a bitline pre-charging function.

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Sense Amplifier for Clocked Array

      A field-effect transistor (FET) is used in this BiCMOS sense
amplifier to rapidly restore a bit line.  The circuit achieves high
performance and low power dissipation on clocked arrays while also
providing a bitline pre-charging function.

      Referring to the figure, N-type transistor T1 conducts during
precharge, thereby charging bit line BL to base emitter potential Vbe
through resistor Rc.  Transistor T1 effectively shorts base node B
and collector node C of bipolar transistor Q1, thereby establishing a
voltage near Vbe on collector node C.  Resistor Rc is made to have a
low value and transistor T1 has a low resistance, therefore a high
performance pre-charge path is provided.

      When an access begins, transistor T1 is not conducting. The
small base current required to sustain bit line BL at Vbe is provided
through resistor Rb while collector C remains near Vbe due to the
small voltage drop across resistor Rb.  If stored data is of such
polarity that storage cell SC does not draw current from bit line BL
when word line WL rises, node C remains at Vbe, which is readily
interpreted as a logical "0".

      If the stored data is such that storage cell SC draws current
from bitline BL when word line WL rises, the current supplied by
resistor Rb is diverted from the base node B of transistor Q1,
thereby turning it off.  When transistor Q1 turns off, node C is
quickly pulled high through resistor Rc, thereby e...