Browse Prior Art Database

Redundant Logic Architecture

IP.com Disclosure Number: IPCOM000120293D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Kemerer, DW: AUTHOR

Abstract

By providing fused access through multiplexors to redundant rows of logic circuits, a large number of circuits may be wired without increasing levels of wiring and high yield of good chips is achieved.

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Redundant Logic Architecture

      By providing fused access through multiplexors to redundant
rows of logic circuits, a large number of circuits may be wired
without increasing levels of wiring and high yield of good chips is
achieved.

      An example of the method is shown in the figure.  Logic books
are placed physically in row 2 with logic service terminals, LSTs,
available for connection as shown.  Row 2 is duplicated in mirror
image as redundant row 4 having redundant terminals, RLSTs.
One-to-two multiplexors 6 are provided for each pair of LSTs.  The
single input of each multiplexor 6 is an input GILST for global chip
wiring. Multiplexors 6 are controlled by a pair of lines row select,
RS, and redundant row select, RRS.  A group of row lines RS may be
controlled by a single chip pad or fuse circuit 8. Inverter I
provides a complement signal to one or more RRS lines for selection
of global input multiplexors 6 and/or global output LST, GOLST,
multiplexors 10.  Multiplexors 6 and 10 are bi-directional.

      This technique can be applied to an entire chip or any portion
of a chip.

      Redundant rows can be controlled by electronically programmable
devices, e.g., scan chain latches, thereby allowing redundancy to be
used at the system level for improved system reliability as well as
to obtain high initial chip yield.

      Disclosed anonymously.