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Browse Prior Art Database

Improved Boundary-Scan Cell for System Outputs

IP.com Disclosure Number: IPCOM000120294D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Oakland, SF: AUTHOR

Abstract

A boundary scan cell for system output signals is described that supports all standard boundary scan operations and leaves no paths untested.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Improved Boundary-Scan Cell for System Outputs

      A boundary scan cell for system output signals is described
that supports all standard boundary scan operations and leaves no
paths untested.

      Referring to the figure, the cell is comprised of two 2-way
selector circuits MA and MB and two latching elements LA and LB.
Element LA has two data input ports.

      The cell supports all standard boundary-scan operations EXTEST,
INTEST, RUNBIST, and SAMPLE/PRELOAD as defined in IEEE Standard
1149.1.  For normal operation, input signal Mode1 is held low,
allowing data from system logic to pass through data path multiplexor
MA to the system output.  This data may be sampled in capture latch
LA and shifted out for inspection without affecting system operation.
For test operations EXTEST, INTEST, and RUNBIST, input signal Mode1
is held high.  Data from system logic may be captured in latch LA if
Mode2 is held low.  Otherwise, data from update latch LB can be
captured.  Thus, any data path can be observed in the boundary latch
in one of the standard test operations.

      There are several alternative implementations of the cell.  For
instance, 2-port latch LA may be replaced by a 2-way multiplexor
followed by a single port latch.  Most other alternatives require
more circuitry.

      Disclosed anonymously.