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Virtual Ground/VDD Control Circuit for Pseudo Static Pull-Up/Pull-Down Devices

IP.com Disclosure Number: IPCOM000120295D
Original Publication Date: 1991-Mar-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Bechade, R: AUTHOR [+4]

Abstract

To reduce power consumption of static arrays while maintaining minimum circuit area afforded by N-type metal oxide silicon (NMOS), a charge dumping technique is used to enable pull-up and pull-down devices during normal operation and test, and to disable pull-up and pull-down devices when a clock is inactive. This virtual ground/high supply voltage (VDD) eliminates DC stand-by power consumption completely in an idle mode.

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This is the abbreviated version, containing approximately 100% of the total text.

Virtual Ground/VDD Control Circuit for Pseudo Static Pull-Up/Pull-Down
Devices

      To reduce power consumption of static arrays while maintaining
minimum circuit area afforded by N-type metal oxide silicon (NMOS), a
charge dumping technique is used to enable pull-up and pull-down
devices during normal operation and test, and to disable pull-up and
pull-down devices when a clock is inactive.  This virtual ground/high
supply voltage (VDD) eliminates DC stand-by power consumption
completely in an idle mode.

      Referring to the figure, clock signal CLK and its complement
CLKN gate NMOS devices T3 and T4.  Capacitor C is discharged when
transistor T4 is on.  Capacitor C is designed to have much larger
capacitance than the capacitance of wire W and the gate of transistor
T5.  Charge on line W and gate of transistor T5 is reduced by
charging capacitor C when transistor T3 is on.  Action of transistors
T3 and T4 permits stopping the clock in any state without affecting
functionality of the circuit.    Transistor T1 is a very small
pull-up device that is enabled by having input TI set low during
normal operation, thus providing a leakage path to shut off
transistor T5 when clock CLK is not active. During LSSD testing, test
input TI is high to force ground on wire W, even when active clock
CLK is pulsed infrequently.

      Disclosed anonymously.