Browse Prior Art Database

Dynamic Remapping of Bad Memory Segments During Power-On Self-Test in a PS/2 System

IP.com Disclosure Number: IPCOM000120320D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 60K

Publishing Venue

IBM

Related People

Massoudian, K: AUTHOR [+3]

Abstract

Disclosed is an algorithm for use in the Power-On Self-Test (POST) of PS/2* to enable and disable memory segments dynamically as they are tested and verified. The IBM PS/2 systems have special code in their ROM modules (ROS) that perform the POST. Part of POST is the memory test which first determines the size of memory present and then does an extensive read/write test to the memory.

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This is the abbreviated version, containing approximately 52% of the total text.

Dynamic Remapping of Bad Memory Segments During Power-On Self-Test
in a PS/2 System

      Disclosed is an algorithm for use in the Power-On
Self-Test (POST) of PS/2* to enable and disable memory segments
dynamically as they are tested and verified.  The IBM PS/2 systems
have special code in their ROM modules (ROS) that perform the POST.
Part of POST is the memory test which first determines the size of
memory present and then does an extensive read/write test to the
memory.

      In the past, if any errors were found during the memory sizing
or testing, the algorithm would just quit and set the memory size to
the last good block of memory.  This would happen in spite of the new
capabilities of the memory controllers in PS/2 systems, which allowed
memory to be enabled and disabled on predefined boundaries (i.e., one
megabyte boundaries) and automatically remapped the addresses to form
a contiguous block of memory.

      In some newly developed PS/2 systems, the memory controller
chips provide the capability for enabling and disabling the planar
memory on one megabyte boundaries. They also allow for 640K split and
ROM-to-RAM remapping. This article describes a new algorithm
developed for POST, which incorporates the new capabilities of memory
controllers, to dynamically map out the bad memory segments and
automatically adjust the user available memory size. With this new
algorithm, once POST is finished, all the available good memory will
be enabled and ready...