Browse Prior Art Database

Incorporation of LSSD in PLCAs

IP.com Disclosure Number: IPCOM000120330D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 151K

Publishing Venue

IBM

Related People

Blum, A: AUTHOR

Abstract

This article relates to the incorporation of LSSD (level-sensitive scan design) in programmable logic cell arrays (PLCAs).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Incorporation of LSSD in PLCAs

      This article relates to the incorporation of LSSD
(level-sensitive scan design) in programmable logic cell arrays
(PLCAs).

      In VLSI, "design for testability" concepts, such as LSSD, have
proved valuable not only for efficient VLSI chip fabrication testing
but also in the debug and the bring-up phase of a logic circuit
design, as well as for system failure diagnostics.

      The PLCAs (Fig. 1) are fabricated to facilitate VLSI 1 micron
feature size and thus can be regarded as VLSI circuits.  Although
chip fabrication testing can be readily performed by controllable
interconnection switches of the PLCAs, there is no access means to
the internal storage elements for the debug and the bring-up phase.

      For implementing scan concepts, such as LSSD, certain
requirements have to be met.  For serial scan via shifting, as is the
case in LSSD, master/slave configurations of flip-flops FFs have to
be used.  The D-type FFs of the PLCAs used in the present concept
each comprise two bistable elements connected in series and capable
of performing the master/slave function required for serial shifting.

      To incorporate LSSD capabilities in PLCAs, the following
hardware changes for extensions have to be made:
1.   The enable clock block of Fig. 1 has to be provided with an
additional controllable interconnection switch (Fig. 2) for forcing a
"0" at the output of this circuit.
2.   The configuration memory cells controlling the activation of the
switches have to be set/reset independently of the remainder of the
configuration memory shown in Fig. 3.

      The PLCA/LSSD activation procedure can be accomplished by:
a.   Stopping the function system clocking.
b.   Setting all clock enable blocks to "0" by a partial reload of
the configuration memory for the clock enable portion without
changing the remainder of the configuration memory (without reset
and/or power drop).
c.   Upon completion of b., reloading the remainder of the
configuration memory to form an LSSD chain without changing the
configuration cells set in b.  In the course of this process, all
FF-clocks will also be connected to a...