Browse Prior Art Database

Bypass Bus Mechanism for Direct Memory Access Controllers

IP.com Disclosure Number: IPCOM000120331D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 198K

Publishing Venue

IBM

Related People

Chisholm, DR: AUTHOR [+4]

Abstract

Described is a bypass bus mechanism for direct memory access (DMA) controllers, as used in personal systems equipped with Micro Channel*. The bus mechanism allows data to be transferred between a DMA controller and an implicitly addressed input/output (I/O) port attached to a microprocessor bus to exchange data without interrupting the microprocessor bus operations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Bypass Bus Mechanism for Direct Memory Access Controllers

      Described is a bypass bus mechanism for direct memory
access (DMA) controllers, as used in personal systems equipped with
Micro Channel*.  The bus mechanism allows data to be transferred
between a DMA controller and an implicitly addressed input/output
(I/O) port attached to a microprocessor bus to exchange data without
interrupting the microprocessor bus operations.

      For comparison purposes, Fig. 1 shows a general-purpose block
diagram of interfacing controller functional components without a
bypass bus mechanism, while Fig. 2 shows the components with a bypass
mechanism included.

      In the prior art of Fig. 1, bus controller 10 includes a DMA
channel (DMAC) function for transferring data in various directions
between an adapter card's microprocessor bus memory 11 and I/O
address space and a computer system's Micro Channel memory (not
shown).  To support this function, bus controller 10 is capable of
acting as a bus master on either the Micro Channel or the
microprocessor bus.  Bus mastership on the Micro Channel is obtained
by asserting PREEMPT and participating in the ensuing bus arbitration
cycle when ARB/GNT goes high. When the bus controller 10's
programmable ARB(0...3) value is equal to or of a higher priority
than the Micro Channel ARB(0...3) value, it assumes Micro Channel bus
mastership and performs data transfers to or from an addressed memory
slave or I/O slave.

      The DMAC has address counters and a data transfer counter.  It
either fills or empties bus controller 10's data buffer, depending on
the direction of transfer that bus controller 10 has been programmed
for.  When the data buffer has been filled, or emptied, bus
controller 10 releases control of the Micro Channel and asserts HOLD
to gain control of the microprocessor bus.  The adapter card
microprocessor releases control of the microprocessor bus and signals
this by asserting HLDA.  Bus controller 10 assumes bus mastership of
the microprocessor bus and performs read or write cycles, that
explicitly address memory address space or I/O address space, to
empty or fill the data buffer from the addressed source and then
releases control of the microprocessor bus by negating HOLD.  Bus
controller 10 continues this sequence of filling or emptying the data
buffer on the Micro Channel and microprocessor bus until the total
data transfer is complete.

      Whenever bus controller 10 assumes bus mastership on a bus, it
prevents other bus masters from using that bus. Specifically,
whenever bus controller 10 moves data across the Micro Channel during
a DMAC transaction, all other Micro Channel bus masters are held off
from performing bus cycles.  Also, whenever bus controller 10 moves
data across the microprocessor bus during a DMAC transaction, the
adapter card's microprocessor is held off from performing bus cycles.
On the microprocessor bus, this is commonly referred to as...