Browse Prior Art Database

High-Speed, Low-Power ECL Circuit With a Darlington-Like Transient Current Source And Active-Pull-Down Driving Stage

IP.com Disclosure Number: IPCOM000120332D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Chuang, CTK: AUTHOR

Abstract

Disclosed is a Darlington-like configuration for a transient current source and the active-pull-down transistor to improve the power-delay performance of the ECL circuit together with a biasing scheme which completely eliminates additional biasing devices/power.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High-Speed, Low-Power ECL Circuit With a Darlington-Like Transient
Current Source And Active-Pull-Down Driving Stage

      Disclosed is a Darlington-like configuration for a
transient current source and the active-pull-down transistor to
improve the power-delay performance of the ECL circuit together with
a biasing scheme which completely eliminates additional biasing
devices/power.

      Recently, various active-pull-down schemes have been invented
to reduce the power consumption and enhance the speed of ECL circuit
(1,2,3).  While these schemes reduce the DC power consumption of the
emitter-follower stage and improve the pull-down delay owing to the
large transient pull-down current, substantial power consumption is
still needed in the logic stage (current switch) to achieve fast
switching.  Moreover, additional devices are needed to implement the
biasing circuit for the active-pull-down transistor and the power
consumption for the biasing circuit is wasted.

      In ECL circuits, the current source can be implemented either
by a resistor or by a transistor current source as shown in Fig. 1.
In the present scheme (Fig. 2), an additional transistor QS is added
which, together with the input transistor Q1, forms a Darlington-like
configuration. Resistors RS1 and RS2 not only act as the steady-state
current source but also form the biasing circuit for QS such that QS
is biased at near cut-in condition (with essentially no DC current)
when the input is 'Low'.  When the input rises to 'High', the voltage
at node A follows immediately once the input crosses the reference
voltage, resulting in transient overdrive at the base of QS and,
hence, large dynamic current for fast pull-down of node C.  Notice
that while the loading at node C is increased due to the capacitance
associated with the collector of QS, the large dynamic current
...