Browse Prior Art Database

Copper Multilevel Interconnections

IP.com Disclosure Number: IPCOM000120352D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Cuomo, JJ: AUTHOR [+4]

Abstract

This disclosure describes the process steps and structures for fabricating Cu interconnections.

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This is the abbreviated version, containing approximately 100% of the total text.

Copper Multilevel Interconnections

      This disclosure describes the process steps and
structures for fabricating Cu interconnections.

      The proposed structures are shown in Figs. 1(a) and 1(b).  The
insulator overlaying the devices and device isolation, and Ti/TiN/CVD
W contact studs formation are the same as in the previous process
[*].  The first Cu conductor is patterned by dry etching (e.g.,
nitrogen/argon ion milling).  Low dielectric materials, such as
polymers, SiO2, etc., can be used for the main insulating materials.
Planarization of the insulator method can be applied, if it is
necessary.  After this, two different methods can be applied at or
above the first metal level:  1) after inter-via level dielectric
material etching, the metal Ta/Cu/Ta trilayer film is deposited; the
second Cu lines and vias are patterned in dry etching, and  2)  the
via and second metal level can be made by the Cu etching technique.

      Reference
-*-  D. Moy, M. Schadt, C-K. Hu, F. Kauman, E. Baran, and D. J.
Pearson, Sixth Int. IEEE VLSI Multilevel Interconnection Conf., 26
(1969).