Browse Prior Art Database

Method of Resolving Multiprocessor Data Integrity Through On-Line Compares

IP.com Disclosure Number: IPCOM000120353D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 107K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

A technique is described whereby data integrity is resolved in a sharing environment by means of performing on-line compares when refetching data. The concept involves the optimization of buffer usages in a sharing environment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method of Resolving Multiprocessor Data Integrity Through On-Line
Compares

      A technique is described whereby data integrity is
resolved in a sharing environment by means of performing on-line
compares when refetching data.  The concept involves the optimization
of buffer usages in a sharing environment.

      In multiprocessor systems which utilize very large caches,
cross- interrogates (XIs) may cause extra cache misses and wipe out
most of the benefits of the large caches.  Normally XI-invalidates
are performed on a line (or block) basis.  That is, if processor Pi
stores into a line L, copies of L will eventually be invalidated from
the remote caches.  As a result, such a remote processor Pj accesses
L later and will end up with a cache miss.  Some trace analysis shows
that fetches to an XI-invalidated line from a processor need not
always right away access the units (e.g., bytes) that were actually
modified by the remote central processors (CPs).  As a result, upon
remote stores, a cache may retain the line and allow faster accesses
later. More straightforward implementation of such a mechanism
involves tagging (and transmitting) of stored units in EX lines.  The
concept described herein provides such a means by way of on-line data
compares.

      For illustration purposes, consider the more conventional
multiprocessor cache design with INV and valid states.  L1s are
store-thru to L2 or main memory (which is shared by all CPs).
Consider also another state - Potentially Dirty (PD) for cache lines.
As usual, fetches to RO or EX lines are granted unconditionally,
while stores are unconditional only to EX lines.  Results of the
executions, depending on conditional storage accesses, should be
subject to possible back-ups.  Situations that require special
handling are as follows:  (When convenient subscripts are used to
label the line covered by a state. First consider the transition of
cache line states).

      Now consider the handling of remote signals (on L) at the cache
control of, say, Pi.
  (a) If a remote CP is requesting XI-invalidate on L owned valid or
PD by Pi - Pi gets PDL (if found in cache).

      Then consider an access, at Pi, to L that is PD in its cache.
  (b) The access is conditional.  Results of executions depending on
such access should be subject to proper back-up when the data used is
found invalid later.  The cache control of Pi will issue a request
(e.g., to the storage controller) for an up-to-date copy of the line
(e.g., from L2, main memory or from other caches).

      Now consider the process of integrity checking of ac...