Browse Prior Art Database

Single Copy State in Multiprocessor Caches

IP.com Disclosure Number: IPCOM000120361D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

A technique is described whereby a single copy (S) state provides control consistency for multiprocessor (MP) caches.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Single Copy State in Multiprocessor Caches

      A technique is described whereby a single copy (S) state
provides control consistency for multiprocessor (MP) caches.

      MP cache coherence control often involves XI-invalidations of
remote lines upon stores.  Consider an L1/L2 hierarchy in which L1'
are store-thru to L2.  Some designs record EX status in the L2
directory.  when the storage control element (SCE) finds a stored
line EX for the requesting central processor (CP), (there is no need
to do a XI-invalidate to remote CPs).  However, when the SCE does not
keep track of the EX status for a long period of time (e.g., with
smaller lock tables), the exclusivity information is often lost and
results in excessive XI-invalidate signaling.  The concept described
herein initiates a state called Single Copy (S) for cache lines. The
S states are maintained by a directory at the SCE(s). One possibility
is to record S states in L2 directories.

      In the following, it is assumed that both fetches and stores
from a processor will require the line be in the L1 cache (otherwise
a miss fetch results):  it is assumed that the SCE keeps a directory
D (which may be part of the L2 directory, or may be a separate one)
in which it records the S states of cache lines in L1.  When a line
L is in the S state, it means that at most one CP may have
it in its cache(s).

      In the following, it is assumed that the S states are recorded
in L2 directories and that the L2 block size is "b" and that L1 line
size is "n".  (Normally "b" is a multiple of "n").  Also, it is
assumed that the SCE uses one extra bit (called the S-bit) per line
in its blocks (e.g., when b=1k and n=64, the SCE maintains 16 bits
per block entry in the L2 directory).  A line is in the S state when
its corresponding S-bit is ON:
   (1) When a block B is first fetched into L2, all of...