Browse Prior Art Database

Highly Reliable Computer Memory Circuit With Battery Backup

IP.com Disclosure Number: IPCOM000120363D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 182K

Publishing Venue

IBM

Related People

Dishon, Y: AUTHOR

Abstract

A technique is described whereby a highly reliable computer memory circuit, with battery backup, assures retention of data in semiconductor memory devices, such as dynamic random access memory (DRAM) modules. Circuits are provided to reliably sense and to switch over to a battery supply should main power fail. Backup power modules are provided in case the main or local battery-supplied power should fail.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Highly Reliable Computer Memory Circuit With Battery Backup

      A technique is described whereby a highly reliable
computer memory circuit, with battery backup, assures retention of
data in semiconductor memory devices, such as dynamic random access
memory (DRAM) modules.  Circuits are provided to reliably sense and
to switch over to a battery supply should main power fail.  Backup
power modules are provided in case the main or local battery-supplied
power should fail.

      Generally, DRAM modules are fabricated using complementary
metal oxide semiconductor (CMOS) materials to achieve the highest bit
storage density per chip.  Also, control logic circuits and refresh
circuits are readily integrated onto a chip.  Further, CMOS
technology requires a minimum of electrical power consumed per bit.
It is known that memories fabricated with CMOS do not retain the data
stored in them when power is removed.  Therefore, some memory systems
provide battery backup power in the event of main power failure.
Such backup power is usually provided centrally, either at the card
(or other chip carrier package) levels, or at the system unit level,
(i.e., the frame that contains the cards, boards, power supply,
etc.). The disadvantage of such a method is that the backup battery
supply itself is vulnerable to failure.

      The concept described herein provides battery backup at the
module level (i.e., the package unit of the chip). Sensors are
provided that reliably switch in the battery backup to the chip in
case of a main power failure. Furthermore, the circuit provides a
backup in case of a local battery failure.  Circuits are provided
that switch in the battery power of other modules, instead of a
failed local battery.  This method can readily be extended for static
random access memories (SRAMs), as well as other memories types.

      A DRAM device with battery backup module controls is shown in
Fig.  1.  Battery power unit 10 provides power to the DRAM during
external main power outage.  This is referred to as "local standby
power".  Main sense circuit 11 senses the availability of main power
and signals when the main voltage supply decreases to a prescribed
voltage level below normal.  The output of the sensor circuit 11 is
also supplied to other chips and is designated as "Main Sense Out".

      Voting circuit 12 functions as a voting control to tabulate the
inputs of main sense circuit 11 and two inputs from the main sense
circuitry of two other DRAM modules (not shown).  If the majority
indicates a loss of main power, the output of voting circuit 12
activates "Standby ON" circuitry.  In addition, the host system is
notified.  If the local main sense circuit is in the minority, it is
disabled by voting circuit 12 and this result is made available to
the system on the main sense disabled line. Voting circuit 12 is
powered from the main, or the standby supplies.

      When "Standby ON" is active, further read...