Browse Prior Art Database

Method of Providing Multiple Page Translation Information

IP.com Disclosure Number: IPCOM000120369D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 3 page(s) / 109K

Publishing Venue

IBM

Related People

Liu, L: AUTHOR

Abstract

Described is a mechanism that provides a lookaside table for computer processors, whereby each entry contains multiple page translation information. The intent is to minimize performance overhead.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method of Providing Multiple Page Translation Information

      Described is a mechanism that provides a lookaside table
for computer processors, whereby each entry contains multiple page
translation information.  The intent is to minimize performance
overhead.

      Advances in numeric computation and parallel processing, etc.,
have necessitated improvements in computer processing techniques.
The concept described herein addresses problems due to translation
lookaside buffer (TLB) misses.

      In prior art, mechanisms have been initiated for translating
multiple page table entries upon each TLB miss. The concept described
herein also provides a structure for the TLB; however, each entry is
deeper with the multiple real frame address sharing common
information, identifying the segment/page for consecutive virtual
pages.  Provided is a lookaside table (TLBL) for a regular TLB such
that each entry in the TLBL may record multiple translation
information.

      For any TLB design, a separate TLBL is structured as a TLB-like
directory, but with few (e.g., 2-8) entries.  For illustration
purpose, each entry has the format:
   TF  STO  SX  BX  PFRA1 . . . PFRAN  C  P
where N is a fixed number.  In certain computer architectural
environments, such as the IBM System/370, each page table has a
maximum of sixty-four page entries.  Then N should be a power of two,
but no bigger than sixty-four. Each PFRAi, 1&i&N, is a real page
frame address along with a valid bit Vi (not depicted).  All pages
covered by a TLBL entry belong to a single segment.  BX is the Block
Index indicating which chunk of consecutive N entries in the relevant
page table this TLBL entry covers.

      Each translation request from the I/E-units is sent to both the
TLB and the TLBL.  Therefore, there are three possibilities:
   (1) If a valid entry is found in just one of them, the valid PFRA
is sent out (e.g., to cache control).  If the valid entry is found in
TLBL, a new entry is created in the TLB and the translation
information is fetched from the TLBL. However, if the valid entry is
found in the TLB, no change is made on the TLBL.
     (2) If in both the TLB and the TLBL valid entries are found
(they should contain identical PFRA in this case), one or both of
them is gated out (depending on the design).
     (3) If the virtual page misses in both TLB and TLBL, the usual
translation processes will be in effect (to look up segment and page
tables).  New entries are created at both the TLB and the TLBL.  A
new entry is not needed if there is already one.  For instance, it is
possible that a block entry is already in the TLBL, but with
particular PFRAi invalid (i.e., Vi is OFF).

      When the page table is loc...