Browse Prior Art Database

Multiple Serial Port Input/Output Handler

IP.com Disclosure Number: IPCOM000120370D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 150K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+4]

Abstract

Described is communications architecture that implements high-speed transmit and sampling registers in conjunction with an intelligent digital signal processor (DSP) to handle multiple serial input/output (I/O) ports for asynchronous (ASYNC) and bisynchronous (BISYNC) communication lines. This allows up to sixteen communication channels to run simultaneously. Flexible switching between protocols is achieved by using DSP-based software (*).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 41% of the total text.

Multiple Serial Port Input/Output Handler

      Described is communications architecture that implements
high-speed transmit and sampling registers in conjunction with an
intelligent digital signal processor (DSP) to handle multiple serial
input/output (I/O) ports for asynchronous (ASYNC) and bisynchronous
(BISYNC) communication lines. This allows up to sixteen communication
channels to run simultaneously.  Flexible switching between protocols
is achieved by using DSP-based software (*).

      Generally, the number of serial ports supporting a circuit card
is limited due to the space requirements for implementing
hardware-based serial I/O handlers.  Serial I/O devices, which
support RS232C, or RS422 interfaces, typically use universal
synchronous asynchronous receiver transmitters (USARTs) or protocol
controllers to implement ASYNC, BISYNC, synchronous data link control
(SDLC), etc., types of protocols.  Normally, the performance criteria
is based on:  a) the maximum baud rate that can be supported per
line; b) the maximum number of serial I/O devices that can be
supported in the desired circuit card space for the I/O card and c)
the maximum throughput of such a card. Also, a desirable feature is
the available intelligence to support special echo characters during
the monitoring of channels.

      The figure shows the component sections of the overall multiple
serial port I/O handler.  Transmit register 10 and sampling register
11 have been added.  The existing handler components are shown below
the dotted line.  Transmit register 10 is a sixteen-bit register
which is periodically loaded.  During the loading period, each
channel (not shown) is allowed to modify the transmit load word for
the channel bit assigned to it.  When multiple synchronous channels
are transmitted with different external clocks, transmit register 10
can be updated more often so as to handle clock skews.

      Sampling register 11 consists of receive data registers and
receive and transmit clock registers.  Microcode examines each bit
with the state of the corresponding bit from the previous sample.
Interrupts occur every 5.2 msec., providing time to execute fifty-two
instructions per interrupt.  Only the edge detection is performed at
the interrupt rate, while the bit and byte processing is performed in
background mode. The average processing time per bit is 52 msec.,
since the input is over-sampled at ten times the bit rate, or 520
instructions/bit.  For synchronous channels and active asynchronous
channels, or when an edge detect operation is performed in microcode,
sampling register 11 is used as an input.

      Microcode architecture [*] is used to implement the multiple
channels.  USART and SYNC character detection is performed in
microcoded algorithms.  The uniqueness lies in the fact that
microcoded USART and SYNC detectors can be used to optimize the
bandwidth usage and achieve maximum throughput across the card.

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