Browse Prior Art Database

Address Translation Mechanism

IP.com Disclosure Number: IPCOM000120393D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Arndt, RL: AUTHOR [+2]

Abstract

Disclosed is a mechanism for translating between a virtual address and a real address within a computer system. This mechanism incorporates a unique access control mechanism which minimizes the hardware required to restrict access to address ranges authorized for the specific requesters.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 98% of the total text.

Address Translation Mechanism

      Disclosed is a mechanism for translating between a
virtual address and a real address within a computer system.  This
mechanism incorporates a unique access control mechanism which
minimizes the hardware required to restrict access to address ranges
authorized for the specific requesters.

      The application is to allow multiple input or output (I/O)
devices to look through a virtual window into the real memory of a
computer system.  The virtual window is further divided into segments
called panes.  Each I/O device is assigned a specific pane in the
virtual window based upon its source identifier.  The virtual address
space is still further divided into pages (the smallest manageable
entity). Each virtual page may be mapped to a page in the computer
system's real memory.  Each virtual page may be marked accessible by
all I/O devices or only accessible by the I/O device assigned to the
particular pane of the virtual window.  By controlling access through
authorized virtual address ranges, access keys are not needed in the
translation control table, this saves a considerable amount of
storage.  Further, the authorized address range for each requester is
determined by a simple mapping of its source identifier.  This
eliminates the base/bound address register pairs per source and an
adder and comparator normally required for address range checking.
The figure is a schematic diagram of an implementation of the address
transl...