Browse Prior Art Database

Process for Planar Double-Poly Bipolar Transistors

IP.com Disclosure Number: IPCOM000120396D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 94K

Publishing Venue

IBM

Related People

Burghartz, J: AUTHOR [+4]

Abstract

Disclosed is a technique which planarizes the emitter polysilicon in a double-poly self-aligned bipolar transistor structure. The process can also be extended to yield a completely planar transistor, thereby simplifying metallization and making it easier to integrate different device structures into the process (e.g., pnp, FET, etc.).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Process for Planar Double-Poly Bipolar Transistors

      Disclosed is a technique which planarizes the emitter
polysilicon in a double-poly self-aligned bipolar transistor
structure.  The process can also be extended to yield a completely
planar transistor, thereby simplifying metallization and making it
easier to integrate different device structures into the process
(e.g., pnp, FET, etc.).

      Current art involves depositing and patterning the emitter poly
near the end of the overall process, leaving a rather severe emitter
topography (Fig. 1a).  This topography can make adequate and uniform
doping of the emitter poly difficult, and will also make
metallization difficult.  To avoid these difficulties, the following
process flow is presented, referring to the figure.

      Standard processing methods are used to provide deep trench
isolation and the planar shallow trench isolation. The polysilicon
for the base contact is deposited, doped and dielectrics deposited as
in a standard bipolar process.  The emitters are defined before
patterning the base polysilicon, so that the wafer surface is still
planar during emitter definition.  Rather than using a
photolithography step to define the emitter poly, the excess poly can
be removed through a simple chem-mech polish step, since, aside from
the emitter openings, the wafer is without any topography at this
stage. This leaves a planar emitter structure, as shown in Fig. 1b,
after which the emitter poly can be implanted, and the emitt...