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Use of Standard ACMOS L1/L2 Latches to Provide Testable Asynchronous, Edge-Triggered And Set/Reset Latches

IP.com Disclosure Number: IPCOM000120400D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 181K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+4]

Abstract

This article details variant usages of the standard ACMOS L1/L2 latches. The latches provided by the ACMOS libraries (2E/2S/??) are implemented as two independently clocked latches in a master/slave configuration. It was expected that all who used them would provide two fixed frequency clocks via the CLKGEN or RLMCLK (clock generation) blocks to insure non-overlapping clocks. The latches are level-sensitive only, thus providing testability. The master/slave arrangement requires that the data be latched into the first latch prior to clocking the second.

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This is the abbreviated version, containing approximately 38% of the total text.

Use of Standard ACMOS L1/L2 Latches to Provide Testable Asynchronous,
Edge-Triggered And Set/Reset Latches

      This article details variant usages of the standard ACMOS
L1/L2 latches.  The latches provided by the ACMOS libraries
(2E/2S/??) are implemented as two independently clocked latches in a
master/slave configuration.  It was expected that all who used them
would provide two fixed frequency clocks via the CLKGEN or RLMCLK
(clock generation) blocks to insure non-overlapping clocks.  The
latches are level-sensitive only, thus providing testability.  The
master/slave arrangement requires that the data be latched into the
first latch prior to clocking the second.

      The flexibility provided by the Micro Channel* causes problems
with this clocking scheme.  Micro Channel signals are asynchronous,
edge-sensitive and of varying active length.  The signals which act
as Micro Channel clocks (ADL, S0, S1, CMD and SDSTB) are not
forecastable, not repetitive and, in some cases, of indeterminate
length.  The information sampled by these clocks may be permitted to
become valid after the clock is activated or disappear prior to the
clock's inactivation.

      Upon contemplation of the interaction of the Micro Channel
signals, we determined that certain functions not targeted by the
library were required but not supported. These functions and their
applications are as follows:
      1) Asynchronous, single clock but still level-sensitive.
           - Sampling of bus information signals and data during
valid periods,  e.g. DPAREN, CHCK, ARB(0:3), Data, Data Parity,
Address, Address Parity, APAREN, MNIO, DS16/32, etc.
      2) Edge-Triggered functions with optional asynchronous set or
clear.
           - Flexible clocking of data latches to accommodate the
switch of clocking signals from CMD to SDSTB for streaming data mode.
           - Release of SDR(0:1) as required by streaming data
protocol for slave termination.
           - Error handling, often requiring the asynchronous
set/reset function.
      3) Latches that are edge-triggered with respect to one clock
and level-sensitive for another.
           - Streaming data address, valid with ADL and then the
internal tracking address, incremented with SDSTB rising.
      4) A Set/Reset situation, primarily in control logic, with a
latch for testability.
           - Implementation of CHRDY mediated pacing.
           - Determination if streaming data protocol is applicable
and imminent.
           - Parity error detection.

      As with any deviation from the norm, concerns about testability
must be addressed, since the project's LSSD testing and verification
plans depend on launch and capture capabilities, and absence of
feedback paths.  All feedback paths are broken with latches set up to
flush during functional mode and to operate normally during test.  As
part of th...