Browse Prior Art Database

Multiplexing of Mutually Exclusive Logic Units

IP.com Disclosure Number: IPCOM000120407D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+3]

Abstract

Disclosed is a technique used to save silicon area and to optimize logic usage in a standard cell/macro design environment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 75% of the total text.

Multiplexing of Mutually Exclusive Logic Units

      Disclosed is a technique used to save silicon area and to
optimize logic usage in a standard cell/macro design environment.

      Mutually exclusive logic units of the same type and size
(replication of a given standard cell) can be reduced to one unit
which is then shared by all operations which require it.  For
example, an 8-bit counter can be used to track the number of
load/store data bytes that have been processed and can be used to
provide a fixed hardware delay as a multiple of the base clock
frequency upon a command load/store.  These functions were
implemented as two counters, then reduced to one counter since
concurrent load/store operations are not possible.

      A variant of this involves the use of one latch to retain the
output from many sources.  Not all of the sources are required at a
given time.  Sources that are used concurrently are mapped to
non-overlapping sections of the latch.  Thus, the latch is larger
than required by any one source, but smaller than the sum of all
latches used in a standard methodology because latch area = D*bits +
C where D and C are constants.  C is thus amortized over more bits.
   SCX - Selects path from counter X (X = 1 to 5).  May depend on
other select terms.
      SLX - Selects feedback path from bank X (X = 1 to 5) of the
latch. May depend on other select terms.
      SRAM - Selects path from RAM word.  May depend on other select
terms...