Browse Prior Art Database

Repair Technique for Area Array Solder Interconnections

IP.com Disclosure Number: IPCOM000120432D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 58K

Publishing Venue

IBM

Related People

Foster, RA: AUTHOR

Abstract

A repair technique is described for electronic package assembly elements joined by area array solder interconnections.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Repair Technique for Area Array Solder Interconnections

      A repair technique is described for electronic package assembly
elements joined by area array solder interconnections.

      The subject package configuration is illustrated in the
accompanying figure.  Package element 1 (hereafter called the module)
is joined to package element 2 (hereafter referred to as the carrier)
by a plurality of solder interconnections 3.  Interconnections within
the carrier (not illustrated) are facilitated by the use of hollow
conductive vias 4, e.g., plated-through-holes (hereafter PTH's).

      Consider the event that, on initial joining, one of the solder
interconnections 5 fails to contact and metallurgically "wet" the
surface of the carrier.  The disclosed concept makes this condition
repairable by passing a wire 6 from the back of the carrier, through
the PTH, until it touches the solder.  This wire serves as a wick for
repair solder.  In the absence of the wire the solder will fail to
flow into the PTH.  After repair solder reflow, the wire is trimmed
to the back surface of the carrier.  Without the wire, repair would
necessitate the removal and replacement of the entire module.

      Disclosed anonymously.