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Circuit to Speed Up Propagation Delay From Clock to Output In a Latch

IP.com Disclosure Number: IPCOM000120433D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 31K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+3]

Abstract

Figure 1 shows an edge triggered Latch A and a clock generator as it exists in the CMOS macro library. Figure 2 shows the circuit used to speed up the delay from CLOCK to output. The circuit adds to Latch A a transparent Latch B and a glitchless Multiplexer C (MUX C).

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Circuit to Speed Up Propagation Delay From Clock to Output In a Latch

      Figure 1 shows an edge triggered Latch A and a clock generator
as it exists in the CMOS macro library.  Figure 2 shows the circuit
used to speed up the delay from CLOCK to output.  The circuit adds to
Latch A a transparent Latch B and a glitchless Multiplexer C (MUX C).

      DATA is valid a little before and after the rising edge of the
CLOCK.  Latch B is transparent when the CLOCK is low and holds data
when the CLOCK is high.  Just prior to the CLOCK going high, the DATA
through Latch B is at the input of MUX C.  When the CLOCK rises, MUX
C selects Latch B.

      DATA is latched in Latch A on the rising edge of the CLOCK.
When the CLOCK falls, MUX C selects Latch A.  No glitches are
observed at the output of MUX C because it is a glitchless
implementation.  The delay through MUX C in Figure 2 is much smaller
than the delay through the Clock Generator and Latch A in Figure 1.

      Disclosed anonymously.