Browse Prior Art Database

Register File Update From Another Register File in a Single Cycle

IP.com Disclosure Number: IPCOM000120434D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 43K

Publishing Venue

IBM

Related People

Arimilli, RK: AUTHOR [+3]

Abstract

Disclosed is a circuit to update a register file from another register file in one cycle. This results in improved performance with reduced logic.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Register File Update From Another Register File in a Single Cycle

      Disclosed is a circuit to update a register file from another
register file in one cycle.  This results in improved performance
with reduced logic.

      Figure 1 shows three register files - Channel Status Register
(CSR), Cache Buffer Control Register 4 and the Cache Buffer Control
Register 8.  A four-bit field in the CSR is used to address 1 of 16
words from Cache Buffer Control Registers 4 and 8.  During an error,
26 of the 32 bits in Cache Buffer Control Register 8 are moved to the
CSR.  As seen in Figure 1, there exists a race, since the 4 bits in
the CSR will change and address another word in Cache Buffer Control
Register 8.

      One implementation is to latch the contents of Cache Buffer
Control Register 8 in a 26 bit latch in the first cycle and then
latch it in the CSR in the second cycle.  The circuit in Figure 1
uses a 4-bit latch and updates the CSR in one cycle.  Figure 2 shows
the control signals used to write the CSR.  The write to the CSR
occurs with WEN=1 and CLOCK=0.  The rising edge of WEN latches the
4-bit address in Latch A and WEN=1 selects Latch A input of MUX B.
Thus, the address to Cache Buffer Control Register 8 is held until
WEN changes to 0 and the CSR is updated in one cycle.

      This improves performance and uses less logic (4-bit latch
instead of 26-bit latch).

      Disclosed anonymously.