Browse Prior Art Database

Partitioned Functional Test During Initial Program Load

IP.com Disclosure Number: IPCOM000120438D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Cheng, C: AUTHOR [+4]

Abstract

Disclosed is the method for functional testing during initial program load (IPL).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Partitioned Functional Test During Initial Program Load

      Disclosed is the method for functional testing during initial
program load (IPL).

      Processor complex checking during IPL is typically done by
either hardware or software.  Processor complexes require all
instruction sets used by the compiler to be tested. Since the
instruction test requires good memory area and since the memory test
requires certain instruction sets to be fully functional, the
disclosed solution here is to test a subset of all the instruction
sets that will be used by the rampost before testing a small memory
area.  Stop IPLing if instruction set testing fails.  Store memory
test results on storage device, such as NVRAM, for future
referencing. After the rampost gets control, it will look in the
proper area in the aforesaid storage device and know where the good
memory can be used to load all the IPL code from the read-only-memory
(ROM).  After the IPL code gets loaded into the memory, the processor
will execute the ROM code at a much faster speed (compared to the
situation where the processor has to execute the code off the ROM
chip).  After the rampost successfully completes its job, it can pass
the control to the second half of the processor complex test where
the rest of the instruction sets can be tested in the memory
environment.

      Through this arrangement, a fast and reliable IPL is achieved.

      Disclosed anonymously.