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Twisted Bit Line Method Requiring no Extra Reference Cell Overhead

IP.com Disclosure Number: IPCOM000120444D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 39K

Publishing Venue

IBM

Related People

Galbi, DE: AUTHOR [+3]

Abstract

By combining two types of transfer device selection patterns by the wordlines in a dynamic random access memory (DRAM) array, the need for additional reference cells is minimized when using a half-twisted bit line (BL) arrangement for reduced BL to BL coupling noise.

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Twisted Bit Line Method Requiring no Extra Reference Cell Overhead

      By combining two types of transfer device selection patterns by
the wordlines in a dynamic random access memory (DRAM) array, the
need for additional reference cells is minimized when using a
half-twisted bit line (BL) arrangement for reduced BL to BL coupling
noise.

      Referring to the figure, twist patterns of true/complement
(T/C) bit line pairs BL1, BL2, and BL3 are the same as in a standard
twisted bit line array wherein wordlines (WLs) make contact to gates
of transfer devices in the pattern shown in Regions 1 or 3 over the
entire array. In this new method, a second pattern of word line
contacts of wordline pairs WL3 and WL4, as shown in Regions 2 and 4,
is alternated with the standard pattern used for wordline pairs WL1
and WL2 shown in Regions 1 and 3.

      The usual fourfold increase in reference cells required in the
standard twisted bit line array is avoided by this new wordline
configuration.  Thus, total area occupied by an array designed by the
new method is substantially less than the area of the same array
designed in the manner of a conventional twisted bit line design.

      Disclosed anonymously.