Browse Prior Art Database

Test Structure and Method for Determining Processing Effects on FETs

IP.com Disclosure Number: IPCOM000120445D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Sayala, M: AUTHOR

Abstract

By making two identical ring oscillator circuits in close proximity to each other on a semiconductor wafer, effects of processing on devices in the ring may be sensitively tested. For instance, process effects on devices having floating gate structures vs. devices having gates tied to a potential or a capacitance may be determined as being the same or different by measuring frequency of oscillation or delay time for a pulse to propogate through the ring.

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Test Structure and Method for Determining Processing Effects on FETs

      By making two identical ring oscillator circuits in close
proximity to each other on a semiconductor wafer, effects of
processing on devices in the ring may be sensitively tested. For
instance, process effects on devices having floating gate structures
vs. devices having gates tied to a potential or a capacitance may be
determined as being the same or different by measuring frequency of
oscillation or delay time for a pulse to propogate through the ring.

      Referring to the figure, a pulse is applied at IN to OR circuit
2 to start the ring circuit comprised of a series of inverters I1,
I2, I3, I4, and OR 2.  Appropriate test pads, e.g., P, may be
included as desired.

      A second ring circuit is constructed nearby of identical
devices but having gates connected to a high capacitance as early as
possible in manufacturing as opposed to the first ring circuit having
devices with gates floating throughout processing.  By probing at pad
P, oscillator frequency or total circuit delay may be determined.
Any small difference in delay characteristics of the series of
devices in the ring circuits is sensitively detected.

      Disclosed anonymously.