Browse Prior Art Database

Combination Input Output Pin for LSSD Testing

IP.com Disclosure Number: IPCOM000120446D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Faucher, MR: AUTHOR [+2]

Abstract

By appropriate design of chip scan input/output (I/O), the number of I/O pins devoted to testing of level-sensitive latch design (LSSD) chips is reduced by 50%.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Combination Input Output Pin for LSSD Testing

      By appropriate design of chip scan input/output (I/O), the
number of I/O pins devoted to testing of level-sensitive latch design
(LSSD) chips is reduced by 50%.

      Tester capability to change from a send to a receive mode
during a single tester cycle is used along with chip scan I/O
circuitry shown in the figure to allow combination I/O (CIO) pad 2 to
send and receive data at different times within the same cycle.
Receiver 4 performs normally when valid data is clocked into LSSD
chain 6 by the A clock. Driver 8 is held off by absence of the
B clock input to AND 10.  B clock is routed through OR 12 to output
enable (OE) of driver 8 when test function enable (TFE) is high.
Normal control of driver 8 is through input from normal driver input
(NDI) to AND 14 when TFE is inactive.

      The tester drive is programmed to turn on during presence of
the A clock and to drive the data appropriate for the cycle into pad
2.  The tester drive is then programmed to "Hi Z" (high impedance
state) for the remainder of the cycle to allow the device to drive
back valid data when the B clock goes active.  The tester is
programmed to sample data placed on pad 2 by driver 8 during B clock
up time.

      Disclosed anonymously.