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Browse Prior Art Database

Limited Pluggable Chip Socket Technology

IP.com Disclosure Number: IPCOM000120452D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 36K

Publishing Venue

IBM

Related People

Cistola, AB: AUTHOR [+2]

Abstract

Disclosed is a process for fabricating a a chip socket with limited chip plug in-out capability.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Limited Pluggable Chip Socket Technology

      Disclosed is a process for fabricating a a chip socket with
limited chip plug in-out capability.

      A chip is designed with the I/O pads moved to one edge, and
gold plated for wipe characteristics.  The socket is prepared by
laminating blanket metalized dielectric layers together, the number
of metal layers can equal the number of I/O's on the chip.

      The metal thickness of each layer should be from 1/3 to the
full width of the individual chip pad widths for good chip to socket
alignment and contact.

      The laminate is then sliced cross sectionally to provide a
wiring plane.  The slice thickness of the wiring plane should be
approximately equal to 2 to 3 times the chip thickness for mechanical
strength to hold the chip in compression.

      This wiring plane is grooved perpendicular to the metal planes
to form a slot for the chip to fit into.  See the drawing.  The
machining and photolith of the wire plane can be in configurations
from single-chip mount to multi-chip high density packaging.

      Disclosed anonymously.