Browse Prior Art Database

Hidden Refresh for a Harvard Architecture Data Processing System

IP.com Disclosure Number: IPCOM000120473D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 1 page(s) / 38K

Publishing Venue

IBM

Related People

Carnevale, MJ: AUTHOR [+4]

Abstract

In the Harvard architecture data processing system pictured in the figure, memory is divided into instruction and data store. In the system, separate logic is used to control data store and instruction store. To insure that refresh cycles do not degrade performance, additional signals are sent to the storage control logic.

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Hidden Refresh for a Harvard Architecture Data Processing System

      In the Harvard architecture data processing system pictured in
the figure, memory is divided into instruction and data store.  In
the system, separate logic is used to control data store and
instruction store.  To insure that refresh cycles do not degrade
performance, additional signals are sent to the storage control
logic.

      To prevent refresh cycles from delaying data read and write
operations, the central processing logic sends a signal indicating a
branch has been taken to the data memory controls.  This branch taken
signal causes a refresh cycle to occur during the "dead" cycles while
the instruction store controls are fetching a non-sequential
instruction that is not in the instruction buffer.  Since typically
branches are taken every 10 instructions, virtually all data refresh
cycles are hidden.

      To minimize refresh cycles from affecting performance of
instruction storage, an instruction buffer is used with a feedback
signal indicating the buffer is full.  This allows the instruction
memory controls to complete a refresh cycle while the central
processing unit executes instructions which reside in the instruction
buffer.

      Disclosed anonymously.