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Browse Prior Art Database

Thermal Chip Stack

IP.com Disclosure Number: IPCOM000120478D
Original Publication Date: 1991-Apr-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Miersch, EF: AUTHOR

Abstract

After achieving very high densities on chip, the density of packaged chips measured in chips per cubic cm becomes more and more important when ultimate packaged circuit and machine speeds have to be reached. Presently, mostly one or a maximum of two chips are placed on a chip site of the next level of packaging. The most efficient way so far is to bond chips to a Multi-Layer Ceramic, Multi Chip Module. Normally chips are wire-bonded or tape automated bonded to printed card on board systems.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 68% of the total text.

Thermal Chip Stack

      After achieving very high densities on chip, the density of
packaged chips measured in chips per cubic cm becomes more and more
important when ultimate packaged circuit and machine speeds have to
be reached.  Presently, mostly one or a maximum of two chips are
placed on a chip site of the next level of packaging.  The most
efficient way so far is to bond chips to a Multi-Layer Ceramic, Multi
Chip Module. Normally chips are wire-bonded or tape automated bonded
to printed card on board systems.

      A packaging scheme is described in this publication wherein a
first pair of standard circuit chips are connected together at their
interior surfaces by bonding and thermal interfaces.  A second such
chip pair is mounted on the first pair, stacked back-to-back with a
thermal interface.

      The combined two chip pairs are mounted on a metal chip carrier
with a thermal sink.  The metal chip carrier is connected at a heat
sink.  Other chip pairs may be added to the stack.

      The chip pairs are electrically connected to the metal carriers
by means of known connectors, such as wire bonds (WB), tape automated
bonds (TAB), flex foil edge connectors (FEC) and special edge chips
(SEC).

      By stacking the chips up as described, as is shown in the
figure, much higher chip densities can be achieved.  The figure shows
only two chip-pairs stacked, but higher stacks like 4 chip-pairs,
etc., are achievable.

      The advantages i...