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Offset Binary Simplifies Timing Control in a PRIV Communication Channel

IP.com Disclosure Number: IPCOM000120495D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 4 page(s) / 111K

Publishing Venue

IBM

Related People

Heise, NN: AUTHOR [+2]

Abstract

A partial response channel (PRIV) may be implemented using digital signal processing techniques. A block diagram is shown in Fig. 1.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Offset Binary Simplifies Timing Control in a PRIV Communication Channel

      A partial response channel (PRIV) may be implemented
using digital signal processing techniques.  A block diagram is shown
in Fig. 1.

      An analog readback signal from a transducer is first amplified
by variable gain amplifier (VGA).  The amplifier gain is adjusted by
a gain control feedback loop so that the output signal amplitude is
regulated.  The signal then passes through a passive equalizer, which
shapes the channel response to the PRIV criteria.  Once shaped to
this criteria, intersymbol interference is controlled.  The signal is
further processed by digital techniques after being converted to an
L-bit binary number by an analog-to-digital (A/D) converter.

      Digital processing functions are performed in each of
functional blocks 1,2,3 shown in Fig. 1.  Even though the loops may
appear to be continuous, the computations are performed by
manipulations on L-bit numbers.

      The decoder function processes incoming L-bit numbers according
to an algorithm which decides if the incoming data is likely a one or
a zero.  For the decoder to operate at lowest error rate, the input
signal applied to the A/D converter must be sampled at the correct
instances in time and be normalized in amplitude and frequency
response.

      Gain control and timing (VFO) feedback loops operate to set
correct VGA amplitude and sampling times.  Two functional blocks of
logic compute gain and phase errors. Resultant L-bit representations
of the error      are converted to analog currents by
digital-to-analog converters, D/As.  The currents are integrated by
loop filters Fg and Ft to control the VGA and VFO, respectively.

      When signal amplitude, sample times, and equalization are
correct, the sampled signal of a class IV system may attain only
three normalized nominal values of {+1,0,-1}. The range of the
sampler is -2 to +2, and this range is sub-divided into 2**L
intervals, each of which is represented by an L-bit number.  If L=6,
the sampled value is then represented by 6 bits, and 6-bit arithmetic
is used in computations.
TIMING ERROR CALCULATION

      In the timing control loop most of the gain control arithmetic
proceeds within one clock period.

      A table of bit combinations versus input voltage intervals is
given in the table below.  This system fits well with the topology of
available 'flash' A/D converters.
                        Offset Binary Numbering System
                Bit             Voltage            Complement
                Representation  Range
                111111           >2 V                 000000
                111110          30/16 V to 2 V        000001
                1...