Browse Prior Art Database

Mixed CSEF And Push-Pull Logic Circuit Families

IP.com Disclosure Number: IPCOM000120503D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 5 page(s) / 140K

Publishing Venue

IBM

Related People

Bonneau, D: AUTHOR [+4]

Abstract

These circuit families include standard current switch emitter-follower (CSEF)/cascode circuits and NOR push-pull circuits. The power delay product of the NOR push-pull circuit is 3 times smaller than that of CSEF. Thus, this circuit is recommended to save power or to drive highly capacitive networks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mixed CSEF And Push-Pull Logic Circuit Families

      These circuit families include standard current switch
emitter-follower (CSEF)/cascode circuits and NOR push-pull circuits.
The power delay product of the NOR push-pull circuit is 3 times
smaller than that of CSEF. Thus, this circuit is recommended to save
power or to drive highly capacitive networks.

      A typical push-pull circuit is described in European patent
89480169.5.

      Two realizations are presented:
      a) The first one uses only one power supply for push-pull and
CSEF and will be described thereafter with reference to Figs. 1 and
2.
   b) The second one does not need any reference voltage other than
GND and VBB, and will be illustrated by Figs. 3, 4 and 5.

      In the first realization illustrated in Fig. 1, the current
switch has been designed to be level compatible and power supply
compatible with the previous push-pull circuit. So it uses an
emitter- follower to define the up level. The down level is defined
by the voltage swing on the collector resistance R1 or R3. The swing
is equal to R collector times I current source. So to obtain a
compatible circuit a special reference network provides the current
switch reference and the current in a diode, D2, which is used as
current mirror to realize the current source.

      The equations giving the push-pull signal swing SS:
  VREF=VCC/2 because R6=R7 and D1=D2
  I(D2)=(VCC-2VBE)/(R6+R7)
  I(current switch)=2*I(D2)
  SS=R*I(current switch) with R=R1 or R3 respective for Out
  and In phase output signals.
  SS=2R(VCC-2VBE)/(R6+R7)
  With R=R1=R3=1.278
  and R6=R7=1.121 we obtain:
  SS=1.14VCC-2.28VBE           (1)
  SS=0.92VCC-1.91VBE           (2)

      Equations (1) and (2) giving the signal swing SS, respectively,
of the push-pull and of the current switch are reasonably close to
each other. So the up and down levels of the two circuits have a
similar behavior versus temperature and power supply variations. A
better tuning will not be sought in this advanced study but it is
noticed that an identical behavior  can be obtained by varying the
relative emitter area of D2 and TCS. The optimum point is between 2X
and 3X and can be obtained with device models specially generated for
that purpose.

      On the other hand, the cascode circuit has been rapidly
evaluated through an XOR2, 2 level cascode tree. The circuit is shown
in Fig. 2.

      The reference circuit for REF1 is similar to the CSEF reference
circuit. REF2 is a one VBE shift of REF1. A third diode to VEE=-0.9 V
leaves the rest of the reference network approximately in the same
voltage and current conditions as for the   CSEF reference circuit.
Thus, the same outpu...