Browse Prior Art Database

Self Retriggering Timer

IP.com Disclosure Number: IPCOM000120505D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Bailey, WD: AUTHOR

Abstract

Disclosed is a circuit which implements a timer function without the usual requirements of externally initializing the timer before each use and disabling the timer when not in use. The timer retriggers regardless of whether the timeout value is reached or not and requires no clock gating. The circuit is applicable to various types of timers.

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This is the abbreviated version, containing approximately 53% of the total text.

Self Retriggering Timer

      Disclosed is a circuit which implements a timer function
without the usual requirements of externally initializing the timer
before each use and disabling the timer when not in use.  The timer
retriggers regardless of whether the timeout value is reached or not
and requires no clock gating.  The circuit is applicable to various
types of timers.

      The figure illustrates the circuit applied as a watchdog timer.
The counting element has as its inputs, a clock, an Initialize value,
and a LOAD signal (which causes the Initialize value to appear at the
counter output).  The outputs of the counter are decoded by the
decode logic to generate two signals.  The FEEDBACK signal indicates
that the counter outputs are equal to the Initialize value.  The
TIMEOUT signal indicates that the time interval has expired. The
Initial state, which produces the FEEDBACK signal, is the next
sequential counter state after the Timeout state, which produces the
TIMEOUT signal.

      The load control logic has three basic inputs:  A START signal
defines the beginning of the interval, a STOP signal defines the end
of the interval, and the FEEDBACK signal. The self-retriggering is
accomplished by use of feedback. The Initialize value is decoded at
the output of the counter.  The FEEDBACK  signal feeds back to the
load control logic, forcing the counter to load the Initialize value
into the counter output.  Thus, when idle, the counter output is hel...