Browse Prior Art Database

Memory Bandwidth Enhancement

IP.com Disclosure Number: IPCOM000120510D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Alvarez, RD: AUTHOR [+3]

Abstract

This article describes a circuit that can save one "wait state" on memory operations in a personal computer system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Memory Bandwidth Enhancement

      This article describes a circuit that can save one "wait
state" on memory operations in a personal computer system.

      Processor speeds have grown at a faster rate than memory
speeds.  A major problem for developers is to provide maximum memory
bandwidth and, hence, system performance, with memory that is
relatively slow.  What usually happens is that wait states must be
applied to dynamic random-access memory (DRAM) access cycles.  Many
techniques are available to enhance the performance of a fast
processor accessing slow memory.  These techniques include cache,
page or static column and interleave.  If two contiguous bus
operations are to the same logical page in memory, then the second
access will be a 'page hit' and thus have a reduced number of wait
states on its bus cycle.  If two contiguous bus operations are not on
the same logical page, then the memory must be 'precharged' prior to
access.  This precharge requires an additional wait state.  The
circuit of this disclosure reduces the number of wait states in a
page miss situation and could increase processor to memory
performance by three to five percent over exiting page mode memory
access implementations.

      Memory in the Intel 80386 microprocessor environment is
organized in 256K x 32 banks, using one Mbit DRAMs.  In some
operating systems several Mbytes of memory are required. This means
that the system will have several banks of memory.  In the page mode
...