Browse Prior Art Database

Page Mode Performance Improvement

IP.com Disclosure Number: IPCOM000120512D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Alvarez, RD: AUTHOR [+2]

Abstract

This article describes a circuit for use in a personal computer system which saves a "wait state" on memory page "miss."

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 57% of the total text.

Page Mode Performance Improvement

      This article describes a circuit for use in a personal
computer system which saves a "wait state" on memory page "miss."

      Processor speeds have increased proportionately at a greater
rate than memory speeds.  It can be a problem to provide maximum
memory bandwidth, hence system performance, with memory that is too
slow.  Usually, in such a case, wait states must be applied to
dynamic RAM (DRAM) access cycles. Many techniques are available to
enhance the performance of a fast processor accessing slow memory.
These techniques include cache, page or static column and interleave.
A number of machines perform page mode access to memory.  If two
contiguous bus operations are to the same logical page in memory,
then the second access will be a 'page hit' and thus have a reduced
number of wait states on its bus cycle. If two contiguous bus
operations are not on the same logical page, then the memory is
precharged prior to access.  The precharge requires an additional
wait state.  The circuit disclosed herein reduces the number of wait
states in a page miss situation.  It will reduce bus cycle length by
one wait state under certain conditions.

      In the page mode memory controller implementations the page
mode access may be lost on the following conditions:
1.   page miss memory access in address space up to 16 Mbytes,
2.   memory access over 16 Mbytes,
3.   I/O port read or writes,
4.   refresh,
5.   dire...