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Bus Transfer Device Incorporating Dynamic Bus Sizing

IP.com Disclosure Number: IPCOM000120522D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 87K

Publishing Venue

IBM

Related People

Boldt, GD: AUTHOR [+2]

Abstract

This design provides a high performance hardware transfer facility between two independent subsystem buses. Dual internal buffers are used to allow concurrent transfers on each bus. Performance is enhanced through a dynamic bus sizing algorithm that attempts to perform all transfers with the maximum data word width supported by each bus.

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Bus Transfer Device Incorporating Dynamic Bus Sizing

      This design provides a high performance hardware transfer
facility between two independent subsystem buses.  Dual internal
buffers are used to allow concurrent transfers on each bus.
Performance is enhanced through a dynamic bus sizing algorithm that
attempts to perform all transfers with the maximum data word width
supported by each bus.

      The design incorporates independent data transfer devices for
each bus which allows simultaneous maximum bandwidth operations on
each bus.  Each set of transfers is begun using the maximum data word
width consistent with the length and alignment of the block of data
to be transferred. The design dynamically changes the mode of
addressing the buffer memories depending on the width of the data
transfer accepted by the device on the bus and provides appropriate
data alignment.

      Each bus has a master state machine that controls the operation
of that bus and sends control signals to the internal state machine
that, in turn, controls the buffer memories.  This internal state
machine is called the fill and empty state machine.  The design is
such that the source bus controls the fill portion of the state ma
chine and the sink bus controls the empty portion of the state
machine.  In general, one buffer will be filled by the source bus
while the other buffer is emptied by the sink bus.  When the
appropriate boundary conditions are met, a pointer is switched and
the buffers exchange functions.

      The data buffers are typically set large enough to allow burst
transfers of multiple words of data during each bus transaction.  In
the design illustrated, up to eight 32-bit words can be transferred
in a single operation.  At the start of each bus transaction, an
attemp...