Browse Prior Art Database

Sub 100H Bus Architecture

IP.com Disclosure Number: IPCOM000120528D
Original Publication Date: 1991-May-01
Included in the Prior Art Database: 2005-Apr-02
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Smith, BA: AUTHOR

Abstract

This article describes a processor system design which provides a means to get to critical facilities (registers at I/O addresses below 100H) without having to negotiate the system bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 56% of the total text.

Sub 100H Bus Architecture

      This article describes a processor system design which
provides a means to get to critical facilities (registers at I/O
addresses below 100H) without having to negotiate the system bus.

      There are I/O ports in personal computer (PC) system
environments that are typically associated with system resource
control, e.g., memory, direct memory access (DMA), interrupt, control
registers.  These registers are located below address 100 Hex and
they are reserved for the system (default) processor only.  DMA and
channel masters cannot access them.  Many of the registers have been
partitioned into chips with standard I/O control, DMA, the bus
interface unit (BIU) or equivalents.  In this architecture default
master must typically access the ports via the channel. The processor
has to win the channel in order to read/write the ports and the
accessibility is subject to various faults on the channel which can
prevent the processor from executing the fundamental code required to
get the system into a semi-functional state during the power-on
diagnostics. Accessing the registers also wastes bus and processor
cycles.

      The drawing shows the design disclosed herein in a functional
block diagram.  All accesses to the I/O ports should be from the
processor side of the dual bus or flow through memory/bus
controllers.  As this is typically an 8- or 16-bit bus, the hardware
delta would amount to a single 16-bit bus driver which could be...